Abstracts

Can Algebra Be an API for Parallel Computing?

Martin Berger

University of Sussex, Brighton, United Kingdom

Many HPC algorithms look structurally alike. For example, evaluators for linear temporal logic (widely used in verification), bounded min-plus shortest paths, and truncated formal power series all run the same loop: combine two equal spans, then double the span. Different state, different primitives, identical pattern. What is the abstract structure making this work? Traditionally, one answer is: semirings. That answer is both too strong and too weak. Too strong, because the loop never uses distributivity or a second operation. Too weak, because a semiring does not tell you which map advances a block, what to start from, or how far to go.

We propose a more precise answer. A seeded monoid endomorphism (SME) is a monoid (M, ⋆, e), one endomorphism τ : M → M, and one seed x ∈ M, with the length-N query

x ⋆ τ(x) ⋆ τ²(x) ⋆ ... ⋆ τ^(N − 1)(x).

A single block law,

S_{j + k} = S_j ⋆ τ^j(S_k)

says exactly when regrouping is legal, no commutativity required, and hands the aggregate to any scan library, binary-powering routine, or tree schedule library. The SMEs are proven and cross-checked in Scala. Vector and GPU lowering, layout, memory traffic, and benchmarks are work-in-progress.

I hope to learn from the audience what other algorithms fit the SME pattern.

On Rings Where a Linear Transformation and Its Inverse and Transpose Have the Same Information Exchange

Gianfranco Bilardi

University of Padova, Italy

Linear transformations are considered over finite rings. It is shown that the information exchange of an invertible linear transformation and that of its inverse are equal, for any ring. It is also shown that the information exchange of any linear transformation over a ring and that of its transpose are equal exactly for Frobenius rings. Applications are presented to the Discrete Fourier Transform and to area-time complexity.

Joint work with Carlo Fantozzi.

Accelerators for AI Factories

Jose Castanos

NVIDIA, USA

In AI factories, accelerators take many forms, from simple IP logic embedded in a custom SoC to full rack-scale solutions. They offload compute, network, and storage workloads, as well as a growing set of specialized functions. On the software side, some engines are reached through libraries, some through custom services, and some have their own instruction set and compilers. This profusion of specialized engines, each with distinct costs and benefits, gives developers a wide array of tools — and makes choosing among them a problem in its own right.

This talk surveys the accelerators NVIDIA offers for building AI factories. We review the current Vera Rubin platform: seven chips — the Vera CPU, Rubin GPU, NVLink 6 switch, ConnectX-9 SuperNIC, BlueField-4 DPU, Spectrum-6 Ethernet switch, and the Groq 3 LPU — assembled into five rack-scale systems on a common MGX architecture. We then turn to accelerators emerging for AI inference and the algorithms that motivated them: disaggregated prefill and decode serving under NVIDIA Dynamo, interconnect-agnostic data movement through NIXL, and the tiering of inference context across a memory hierarchy that no longer fits in HBM. Finally, we compare the software architectures these engines expose, and report which accelerators proved most effective in practice — along with several offload engines from earlier generations that did not.

Flow Parallel Processing Unit® architecture and selected algorithms

Martti Forsell

Flow Computing Oy, Finland

Multicore CPUs are workhorses of general purpose computation. They have roots deep down in the end of Dennard scaling, replication of sequential cores with instruction-level parallel execution capabilities and shared memory systems optimized for coherent sequential locality maximized accesses. As a result, multicore CPUs fail to properly address the requirements of efficient parallel execution, including (i) tolerating latencies of shared memory access rising as the number of cores increases, (ii) providing sufficient memory bandwidth for random access, (iii) reducing the synchronization cost of parallel software components down to a sustainable level and (iv) accompanying the hardware with a simple and productive way to write parallel software. The processor community has attempted to address these challenges with SIMD units, vector units, metric units, neural units and GPUs but with limited success. The Flow Parallel processing unit® (PPU) is an accelerator for boosting CPU performance and simplifying the programming of parallel functionalities. Unlike current alternatives, Flow PPU is designed to boost demanding general purpose functionalities.

In this presentation, we will have a look at the architecture of the Flow PPU as well as selected algorithms. Simple examples and early performance and migration results are shown.

Sparse Linear Algebra as a Scalable Computational Paradigm in Life Sciences and Data Analytics

Giulia Guidi

Cornell University, New York, USA

The scale of scientific data is outpacing the tools used to analyze it. Genomics and data analytics often involve irregular computation with data-dependent access and communication patterns whose mapping onto modern machines is challenging, and their code has to be rewritten for each new architecture. This talk presents sparse linear algebra as a portable, high-performance abstraction between these applications and the available hardware, reducing a domain’s computation to a small set of primitives that inherit decades of algorithmic and hardware optimization and shifting architecture-specific tuning to a reusable layer. Clustering expressed as sparse matrix products, and biobank-scale population genetics recast from a graph traversal into a sparse triangular solve, run on these primitives with no custom kernels, turning analyses that once took hours or days on CPUs into minutes on a single GPU node. These examples point to a broader goal, where the sparse abstraction becomes a lens for co-designing the algorithms and hardware that irregular science will need next.

Composable Digital Twins for DevOps in Societal-Scale ICT Infrastructure

Alexandru Iosup

VU University, Amsterdam, The Netherlands

To succeed in the modern digital economy and society, digital services and the societal-scale ICT infrastructure they run on must be planned, built, and managed similarly to, e.g., healthcare, water, and the financial system. Already, modern development and operations (DevOps) create and run the digital services used in scientific and engineering processes, AI-driven smart industry and energy systems and applications, societal applications including urban mobility, user-facing applications such as immersive XR, and many others. DevOps uses standardized processes that lead to good manageability, responsibility, sustainability, usability, and affordability, while taking into account concerns such as privacy, security, and emerging laws and regulations. However, the complexity of modern ICT infrastructure, and increasingly of the DevOps processes themselves, is rapidly exceeding our ability to manage them effectively. Consequences range from wasted resources to unstable operations, from daily unavailability to catastrophic crashes. The renewed focus on ICT sovereignty adds further urgency, requiring techniques for third-party transparency and independent decision-making, and for giving more agency to all stakeholders and citizens.

In this talk, we argue that an emerging technology, Digital Twinning for ICT infrastructure (DT4ICT), offers a promising step toward taming the complexity challenges of ICT infrastructure and related DevOps processes. DT is a general technology with many decades of development, in which virtual replicas of a physical infrastructure are created to mirror the real-time system state, evaluate what-if scenarios, and support informed decision-making. However, ICT systems pose unique challenges for digital twinning, as they are idiosyncratic in their processes, deeply layered, highly dynamic, and composed of heterogeneous components that evolve at different rates. No single model or simulation can capture the full breadth of a modern ICT environment. As a result, building a monolithic DT for ICT infrastructure is neither realistic nor desirable. What is needed is a composable approach where specialized twins for different subsystems and lifecycle stages can be developed independently and integrated on demand. Such composability enables flexibility in modeling, maintainability over time, and operational scalability from a single rack to nationwide infrastructure.

We present results from the past few years on composable DT4ICT, and how they are currently being integrated into DevOps scenarios and teams. We focus on the challenges of transitioning from our advanced simulation platform, OpenDC, to a DT platform, OpenDT, and on how closing the loop and operationalizing this as a service pose important new challenges.

We also aim to find birds of a feather across all (composable) DT4ICT topics, from technical challenges to related societal and economic impacts, focusing on: What is DT4ICT going to look like over the next 2–5 years? What opportunities and challenges emerge in this interval? How will DT4ICT evolve over the next 5–10 years?

We could continue the discussion in the scope of the new DT4ICT activity recently started by the SPEC RG Cloud Group, and related to the national-level project 6G FNS (EUR 315M, 2023–2030). This could also enable us to develop projects together – and apply for the next round(s) of EU funding.

Computing with Waves – An Introduction to Optical Computing and Accelerator Opportunities

Paul Kelly

Imperial College, London, United Kingdom

This year’s ScalPerf theme is accelerators – and we live in a golden age for accelerator architects. This talk is about opportunities for accelerators that might be orders of magnitude faster and more energy-efficient than even the most finely-honed ASIC – we explore optical computing. The talk is not about my own work – my aim is to talk about a selection of provocative, suggestive ideas that hopefully offer a hint that exciting things are possible. We start with computing near or in an image sensor – and add a little optical-domain pre-processing (“freeform pixels”). Then optical diffraction neural networks (ODNNs). Then optical reservoirs. This is not computing as we know it – but when it works, it’s quite exciting.

SkePU-Streaming: Distributed Pipelining of Portable Skeleton-Based Stream Computations

Christoph Kessler

Linköping University, Sweden

We present SkePU-Streaming, a two-layer high-level programming framework for specifying complex pipelines composed of portable multi-backend stream processing tasks, each expressed by algorithmic skeletons or user-provided implementations, and its deployment toolchain for distributed heterogeneous parallel systems. Pipeline tasks can be moldable-parallel and can have multiple implementation variants to more flexibly exploit the resources of heterogeneous nodes. The convenient expression of multi-variant tasks is achieved by integrating the high-level C++-based skeleton programming framework SkePU with its multiple backends as the main method for portable programming of the stream-processing tasks. Concretely, SkePU-Streaming adds an abstraction layer for pipeline workflow specifications atop SkePU-based task specifications. It extends the SkePU data-container API with stream access operators for use within SkePU and other C++ task code. We present the SkePU-Streaming design and its implementation in a deployment framework for distributed heterogeneous parallel systems, and demonstrate its use with two different soft-realtime video processing applications.

Reference: A. Svensson, F. Crugnola, A. Ernstsson, S. Khosravi, S. Litzinger, A. Lindskog, C. Kessler: "SkePU-Streaming: Distributed Pipelining of Portable Data-Parallel Skeleton Computations for the Heterogeneous Edge-Cloud Continuum." Int J Parallel Prog 54, 7 (2026). https://doi.org/10.1007/s10766-026-00814-w

Prompt Engineering for HPC Vibe Coding

David E. Keyes

King Abdullah University of Science and Technology, Thuwal, Saudi Arabia

The title is an exaggeration in September 2026 but is expected to reflect reality within a few cycles of further ingestion of open-source HPC codes by LLMs and research programs like the US DOE’s Genesis Mission. The most sophisticated code and problem transformation agendas of today’s computational scientists are beyond vibe coders presently; however, they warrant systematic examination upon our transition to fused computing, where machine learning joins traditional modeling and simulation as an HPC domain, with synergistic benefits in both directions.

Some imperatives (“prompts”) for performance include: reside high on the memory hierarchy (e.g., by blocking or processing on the fly), reduce synchrony in frequency and/or in span (e.g., by performing extra flops), reduce communication in number and/or volume of messages (e.g., by exploiting extra memory), employ dynamic scheduling and balancing (e.g., by runtime systems based on DAGs), avoid over-resolving with respect to output accuracy requirements (e.g., adapt precision, fidelity, and inner tolerances), reformulate applications before computing (e.g., with smarter bases or discretizations), codesign algorithms with hardware (e.g., specialized heterogeneity in processing, memory, and networking elements), exploit the “right to re-order” (e.g., linearization vs partitioning, lagged evaluations, colorings), exploit hierarchical or multiple alternative versions of the same system, exploit data sparsity to meet “curse of dimensionality” with “blessing of low rank”, take resilience into algorithms, relieving hardware and systems, look “over the transoms” for optimizations beyond optimized components, code to specialized back-ends while presenting high-level APIs to users, consider “science per Joule.” Most are classical but have new significance.

This talk comes downstream of four Gordon Bell finalist papers from KAUST HPC scientists in 2022–2024 and contains fresh examples. Most importantly, it is a solicitation from fellow workshop participants of further and better examples.

RISC-V for Inference: Beating GPU-Native Formats on Performance and Quality

Earl A. Killian

Rhoa Research / Aril

LLM decode is bandwidth-bound: tokens per second is set by the bytes moved per token, so bits-per-weight is not a memory optimization but the primary performance knob. Post-training quantization trades quality for bits – which means a quantization scheme is not a point but a curve, quality as a function of bits per weight, and where that curve sits is the whole question.

A GPU is universal, so the constraint is not capability but cost: the formats it can afford are the ones its functional units already implement. In practice that is a narrow family of block-scaled floating-point – MXFP and NVFP4 – chosen to fit the datapath rather than the weight distribution. The curve is therefore fixed not by what is possible but by what is cheap.

We present Scaled Outer Product (SOP), a matrix extension to the RISC-V Vector ISA that moves that boundary: per-block trained codebooks, dual codebooks, and per-layer bit allocation become a pipeline stage. One curve, read two ways – given a quality target, SOP reaches it at fewer bits per weight, and the memory wall converts those bits directly into decode throughput; given a fixed DRAM and performance budget, the same curve delivers higher quality at that budget. We report measured quality against the GPU-native formats across a range of open models, and describe the pipeline and chip plan that follow from the extension.

On the Significance of Modern Frequency Scaling Drivers for Energy Efficiency in Task Scheduling

Sebastian Litzinger

Linköping University, Sweden

When solving task scheduling problems, Dynamic Voltage and Frequency Scaling (DVFS) can be leveraged as a means to control and predict task runtimes and system power consumption. If the set of available frequencies is small—as has traditionally been the case with AMD’s x86 processors—energy efficiency is seriously threatened. The amd-pstate scaling driver promises continuous frequency scaling on recent AMD systems from the Zen 2 microarchitecture onward, which could relieve these issues. In this talk, we will examine how well these claims hold up in practice, study the impact on CPU power consumption, discuss the implications for energy-efficient task scheduling, and identify subsequent research problems.

How to build a Exascale system in more or less 12 months

Bernd Mohr

Jülich Supercomputing Centre, Germany

The Forschungszentrum Jülich is a leading research institution in Europe, employing over 7,500 people. Its Jülich Supercomputing Centre (JSC) provides supercomputer services and support to national and international user communities. The JSC is the largest of Germany's three national supercomputing centres, with a workforce of over 350. JSC is currently in the final stages of installing Europe's first exascale system, JUPITER, which is expected to be operational by summer 2026. Alongside JUPITER, we are setting up the Jülich AI Factory (JAIF), which is one of 19 AI factories in Europe. This talk will provide insights into the planning and building of the JUPITER Modular Data Centre (MDC), which enabled the construction of an exascale system within 12 months in 2025. The talk will also present the first scientific results from using the centre. Finally, the talk will provide more details of the two planned cluster modules and the AI inference module for JUPITER, which are due to be installed in early 2027. 

Parallel and Hierarchical Transformer Computations 

Silvia Mondin

University of Padova, Italy

Humans Think to Speak; Machines Speak to Think

José Moreira

IBM Research, Yorktown Heights, USA

Human language is commonly viewed as an expression of thought: cognition precedes speech, while language subsequently amplifies cognition by supporting abstraction, memory, planning, and collective knowledge. Modern artificial intelligence appears to invert this relationship. Large language models are trained primarily to predict and generate language, yet at sufficient scale they exhibit behaviors that resemble reasoning, explanation, problem solving, and creativity. This talk explores the provocative hypothesis that, for machines, mastery of language can become a route to thought-like computation. It asks why modeling the linguistic traces of human thought produces systems capable of reproducing many observable products of that thought—and where this analogy breaks down. Finally, the talk connects this phenomenon to specialized hardware: advances in accelerators have made it possible to train and run language models at scales where such capabilities emerge. Machines may “speak to think,” but only because architectures, algorithms, and massive computation make that speech possible.

A Graphical Model for Reinforcement Learning

Keshav Pingali

University of Texas, Austin, USA

Recent advances in AI/ML have resulted in a Precambrian explosion of specialized processors for training and inference. Generating high-performance code for these processors is a challenging problem since we do not have enough experts in high-performance computing, compilers and architectures. To address this problem, researchers are trying to use AI/ML techniques such as reinforcement learning. However, standard narratives of reinforcement learning use complex formulas with expectations and gradients, and are not intuitive. In this talk, we present a graphical model for reinforcement learning that makes it easier to visualize the core algorithms in reinforcement learning, including tabular and policy gradient methods.

Performance Optimization for Accelerators: Potential and Challenges

Saday Sadayappan

University of Utah, Salt Lake City, USA

With the significant slowing of Moore’s Law, technology scaling has become increasingly expensive, leaving hardware customization as the most attractive remaining path to significant future gains in per-chip performance and energy efficiency. While GPUs have dominated the landscape for Machine Learning in recent years, accelerators are now picking up significant momentum. A key advantage of many accelerator architectures over GPUs is the amount of "shareable" on-chip memory, potentially enabling reduced off-chip data movement that is very expensive. However, the problem of mapping and scheduling is more challenging for accelerators than GPUs. Using data points from current GPUs and accelerators, this talk will discuss the potential benefits and the challenges in achieving high performance and energy efficiency with accelerators.

First Experiences When Using ONNX for Scientific Computing

Sven-Bodo Scholz

Radboud University, Nijmegen, The Netherlands

Many new architectures have been created aiming at improved AI computations. These machines promise faster computations or lower power consumption in comparison to standard hardware.

Given that AI computations are mainly based on a small set of linear algebra operations it should be possible to leverage the benefits of these architectures for scientific computation as well. In a first attempt to do so, we look into the feasibility of leveraging Open Neural Network Exchange (ONNX) as an intermediate representation which is supported by a rather wide range of accelerator platforms. This talk presents our first experiences when trying to generate ONNX from scientific applications written in C / SaC.

Fast Matrix Multiplication - Theory and Practice

Oded Schwartz

Hebrew University of Jerusalem, Israel

Matrix multiplication is everywhere: In AI, algo-trading, simulations, graphics and more. AI / deep neural network applications spend up to 95% of the time on matrix multiplication. Matrix multiplication is expected to consume over 1% of the electricity worldwide this year. In recent years, the tech giants responded with high-performance math software (for GPU and CPU) and with hardware accelerators. Yet, all state-of-the-art solutions are based on the wasteful cubic-time classic matrix multiplication algorithm, despite more than five decades of research on sub-cubic time algorithms. Why is that? In this talk I will present a brief history of the ongoing race (of humans and machines) for faster matrix multiplication. How to multiply large matrices and small ones. Dos and don’ts when precision and reproducibility matter. And which of these algorithmic advances can be used in practice.

Algebra as Architecture: Majorana–Paraparticle Logic for Structured-Light Quantum Accelerators

Fabrizio Tamburini

Rotonium Quantum Computing, Padova, Italy

Specialized accelerators are usually defined by their physical substrate, instruction set, and dataflow. We propose that algebraic grading can also become part of the architecture. In the Rotonium framework, a finite truncation of Majorana’s infinite-component tower is organized as a graded paraparticle algebra and mapped onto structured-light modes. Orbital-angular-momentum parity and polarization or spin angular momentum define four grades, forming a photonic ququart—equivalently, two logical binary subsystems carried by one photon. In the ideal intraphoton unitary model, mode conversion and conditional-phase operations implement deterministic CNOT- and CZ-type gates without direct photon–photon nonlinearities or local postselection.

From an accelerator perspective, grades act as state types, optical components as native instructions, selection rules as leakage checks, and compilation as the mapping of circuits onto calibrated mode transformations. We connect this proposal to Rotonium’s room-temperature photonic processors, discuss scaling and benchmarking, and distinguish demonstrated results from open challenges in loss, crosstalk, integration, interphoton operations, and symmetry-based error control.

HPC Tools for the RISC-V HPC Ecosystem: The DARE Project and TUM’s Contributions Revisited One Year Later

Carsten Trinitis

Technical University of Munich, Germany

After another year for DARE, quite a few goals have been reached and new challenges have come up. TUM’s job within DARE is to provide a user-friendly gdb extension for RISC-V-specific parallelism. At the data-parallelism level, the RISC-V Vector (RVV) extension introduces powerful yet complex semantics for data-parallel execution, including dynamically sized vectors and configurable element layouts. Whilst these features offer high performance and portability, they also complicate debugging, as existing tools, such as GDB, do not present RVV registers in a configuration-aware manner. Consequently, raw and verbose register dumps must be manually interpreted relative to the current vector register state. In the first stage within DARE, TUM has implemented a lightweight visualisation tool integrated directly into GDB through its Python API. This approach augments GDB’s Text User Interface (TUI) with a custom register view that dynamically renders vector contents and configuration state during program execution while preserving the familiar GDB workflow. For future matrix extensions, the Integrated Matrix Extension (IME), debugging extensions have been implemented accordingly. The talk will also present a first version of the matrix debugger and give an outlook on integrating it into widely used GUIs such as VSCode.

Hardware-Software Pendulum

Henry Tufo

IBM Research

There have been periods where one or the other have been the primary focus. Lately things seem to have gotten out of whack. A few years back, software was king. Even mentioning hardware brought chuckles of derision. With the rise of AI, a violent swing ensued that called into question the need for significant human effort to develop, maintain, and debug software. This reevaluation wiped billions (perhaps trillions if you properly account for private equity) of market capitalization from those companies deriving a significant portion of their earnings from software. What will it take to bring software back into fashion?

A corollary, which I alluded to last time: are we overinvesting in hardware?

Reducing Waste in GPU Computing

Ana-Lucia Varbanescu

University of Twente, Enschede, The Netherlands

GPUs have the biggest share of the accelerator market, especially given their importance for AI workloads. But are they really the right tool for the job? Under the simplistic definition that "waste happens when a system’s resources are not used efficiently", we investigated the waste in AI workloads, and demonstrated a reduction of more than 15% is feasible in ideal circumstances. We further propose several approaches to reduce waste in GPU computing, analysing their improvement potential and foreseen challenges for practical implementation/deployment.

Automatic Load Balancing via Malleable Runtimes for HPC

Josef Weidendorfer

Technical University of Dresden, Germany

Malleability in HPC applications means that they can cope with dynamic resource changes at runtime, enabling more flexibility for job scheduling. The required functionality for rebalancing work after a resource change also can be used for automatic load balancing on heterogeneous resources. In this talk, we present progress in this direction in an experimental programming model and runtime for malleability. Furthermore, we discuss how this enables resource exchange strategies for dynamic load balancing for coupled codes.